NVIDIA Cuts HBM4 Speed and NVLink Bandwidth Targets for "Vera Rubin

NVIDIA has officially implemented changes across its "Vera Rubin" product line, reducing target specifications for memory and interconnect fabric. According to the updated product specification sheet, the first change involves HBM4 memory. Previously, NVIDIA used HBM4 with a speed of 11.7 Gbps per pin, which has now been reduced to 9.6 Gbps per pin. In a "Vera Rubin" NVL72 rack-scale solution, NVIDIA now offers a total memory bandwidth of 1,400 TB/s, down from the previously advertised 1,580 TB/s. While this issue does not stem directly from NVIDIA's suppliers, it indicates that the company's implementation of memory bus width and overall electrical signaling is insufficient to support higher speeds.

However, the changes are not limited to memory. NVIDIA has also reduced the previously advertised NVLink bandwidth per GPU, decreasing it from 1.8 TB/s to 1.5 TB/s. This results in a reduction from 3.6 TB/s to 3 TB/s in bidirectional NVLink GPU bandwidth. The underlying issue is related to signal integrity, as NVIDIA reportedly lowered the NVLink Nyquist frequency target from 56 GHz to 47 GHz. Lowering the Nyquist frequency reduces the electrical demands on the SerDes, cables, and materials, which can improve manufacturing yields and overall feasibility, even though it requires accepting a small reduction in peak interconnect bandwidth. Thus, NVIDIA chose to sacrifice some bandwidth to enhance system stability. Below is the new system specification in light mode, and old system specification in dark mode. Read full story